Design Engineer – Memory Or Std.Cell Design Full Time

Sankalp Semiconductor offers an integrated portfolio of services and solutions to its customers in key semiconductor domains including analog & mixed signal, digital, high-speed physical interface IP, Embedded Memory Compiler, IOs and EDA modelling. Sankalp Semiconductor is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer, Networking, Wireless, IoT, Medical electronics and Foundry space. The company enables its customers to achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to design System on- Chip. Sankalp Semiconductor is based in Sunnyvale, California, with offices in USA, India, Canada, Germany and Malaysia. www.sankalpsemi.com
About Practice:                                      
Sankalp memory practice deals with memory compiler or instance development from specification to gds. Team has vast experience for development of low power, high performance and/or high density SRAM memories for 5nm to 180nm technologies. Team also has experience of developing flash memories. For development of memory it uses Sankalp’s or client’s memory flow. It has its own memory compiler (MC2).   The project are done in T&M (time and material) or ownership/turnkey mode. The practice serves many client including all top memory players.

Skills Required

• Candidate must possess a minimum of Bachelor Degree in Electrical/Electronic for Memory Characterization and design.
• Candidate must possess a minimum of Diploma or Bachelor Degree in Electrical/Electronic for Memory layout
• 2-8 years of experience in memory design, characterization or layout.
• Hands on experience in 45nm, 28nm or lower process technology for memory layout
• For Memory Layout Candidate should have knowledge of critical design rules, yield and reliability issues (EM-IR, HCI and NBTI).
• Memory Layout Candidate should have working knowledge of layout design and physical verification tools.
• For Memory Layout Candidate should have understanding of deep sub-micron & DFM issues and various layout techniques.
• For Memory Design and Characterization candidate should have transistor level memory circuit design experience and hands on experience in 45nm, 28nm or lower process technologies.

Job Requirements

• Bachelors / Master Degree in E&E and E&C
• Experience : 2 to 8 years
• Strong communication and team work skills
• Job Location : Bangalore / Noida